1. Field of the Invention
The present invention relates to the field of amplifiers having differential input and output, fabricated in CMOS technology with N-channel and P-channel transistors.
2. Discussion Of the Related Art
FIG. 1A schematically shows such an amplifier with differential input and output. A differential amplifier 10 is provided with two symmetrical inputs e.sup.+ and e.sup.- and two symmetrical outputs S.sup.+ and S.sup.-. Generally, a resistive or capacitive load, including a medium tap M, is provided between outputs S.sup.+ and S.sup.-. Voltages S.sup.+ and S.sup.- are symmetric with respect to voltage VM at the lnedium tap M. Such a circuit is coupled between a high supply terminal Vdd and a low supply terminal Vss. If VM is close to one of those limit values, the output voltage range is significantly reduced. Therefore, it is desired that VM is close to an optimal common mode voltage, VCM, that should have a value close to (Vdd-Vss)/2.
This type of amplifier is frequently used in so-called switched-capacitor circuits. An exemplary circuit, forming a conventional integrator, is illustrated in FIG. 1B. This circuit, known per se, will not be described in detail. It should be noted that this circuit includes high frequency controlled switches, some of which, referenced 1, are switched during a first phase of a clock signal, and some others, referenced 2, are switched during a complementary phase of the clock signal. Negative feedback capacitors, Cr, are permanently connected between the complementary inputs and outputs of the differential amplifier 10. Switched capacitors Ca and Cb have values that are much lower than the values of the negative feedback capacitors Cr.
FIG. 2 shows, by way of example, an embodiment of a two-stage amplifier having differential input and output. In the following description, MN designates an N-channel MOS transistor and MP designates a P-channel MOS transistor.
The input differential stage includes two MOS transistors, MN1 and MN2, respectively receiving at their gate the differential input signals e.sup.+ and e.sup.-. The drains of the input transistors are connected, through respective loads, to the high-supply terminal Vdd. FIG. 2 illustrates a cascode-type stage, including two cascode transistors MN3 and MN4 whose gates are connected to a polarization source P1, and two charge transistors MP5 and MP6 whose gates are connected to a polarization source P2. The drawing shows in more detail that the source of MN3 is connected to the drain of MN1, the drains of MP5 and MN3 are interconnected, and the source of MP5 is connected to Vdd. Similarly, the source of MN4 is connected to the drain of MN2, the drains of MN4 and MP6 are interconnected, and the source of MP6 is connected to Vdd. Polarization P1 is applied to the gates of MN3 and MN4, and polarization P2 is applied to the gates of MP5 and MP6.
The outputs of this input differential stage, that are drawn from the common nodes of drains of transistors MN3 and MP5 and of transistors MN4 and MP6, respectively, are amplified by an output differential stage including transistors MP7 and MP8 whose sources are connected to Vdd and the drains to the low supply voltage Vss through respective current sources MN9 and MN10. The gates of transistors MN9 and MN10 are connected to a polarization voltage P3 that is also applied to the gate of a transistor MN11 connected between the common sources of transistors MN1 and MN2 and voltage Vss. The differential outputs S.sup.- and S.sup.+ of the circuit correspond to the drains of transistors MP7 and MP8, respectively.
In CMOS technology using a P-type substrate, each P-channel MOS transistor is fabricated in a well N. Well N is connected to the source of the transistor, that is, frequently, at voltage Vdd.
FIG. 2 also represents the medium tap M between identical output impedances Z1 and Z2. An asymmetry between inputs e.sup.+ and e.sup.- with respect to a predetermined common mode voltage VCM causes an offset of voltage VM at medium tap M with respect to the predetermined common mode voltage VCM.
Capacitors C1 and C2 operate as a stabilization circuit and are respectively connected between the drains of transistors MN1 and MP7 and between the drains of transistors MN2 and MP8.
Those skilled in the art will notice that the circuit is only illustrative of a double differential stage and that many modifications can be made. For example, cascode transistors MN3 and MN4 can be eliminated; then, a series resistor should be added to the stabilization capacitors C1 and C2. Many other variants can be devised to improve the circuit's consumption, or its sensitivity to temperature variations.
To cancel the offset of voltage VM with respect to voltage VCM, realignment circuits, also referred to as common mode negative feedback circuits, are also provided in the prior art.
In the prior art, this negative feedback is often provided at the output stage, which exhibits some drawbacks, among which:
the occurrence of a parasitic negative feedback loop between the output stage and the input stage which involves providing additional stabilization circuits, PA1 the power consumption of the negative feedback stage is not negligible since it has to provide currents as high as the currents in the output stage.
There has also been suggested to provide the common mode negative feedback at the input stage. U.S. Pat. No. 4,697,152 teaches such an approach. The common mode negative feedback is made on the charge transistors of the differential stage. Further to the detection of a common mode offset, one acts on the gates of the charge transistors of each of the differential legs. This solution also presents many drawbacks. First, it introduces a feedback time constant because the gate capacitances of the transistors on which it is acted introduce a delay time. Second, it complicates, or makes it impossible, the use of a charge stage of the cascode-type.
A second solution for introducing a common mode feedback on the input stage is suggested in an article by Roy Batruni, Pierre Lemaitre and Thierry Fensch, published in "IEEE Journal of solid-state circuits", vol. 25, No. 6, December 1990, pp. 1414-1425. This solution avoids the drawbacks relating to the time constant and the difficulty of inserting a cascode stage as in the former solution but presents other drawbacks that will be explained hereinafter.